دانلود رایگان ترجمه مقاله معماری بافر الاستیک برای روترهای شبکه روی تراشه (نشریه IEEE 2014)

ElastiStore: معماری بافر الاستیک برای روترهای شبکه روی تراشه

ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers

Abstract

The design of scalable Network-on-Chip (NoC) architectures calls for new implementations that achieve high-throughput and low-latency operation, without exceeding the stringent area-energy constraints of modern Systems-on-Chip (SoC). The router’s buffer architecture is a critical design aspect that affects both network-wide performance and implementation characteristics. In this paper, we extend Elastic Buffer (EB) architectures to support multiple Virtual Channels (VC) and we derive ElastiStore, a novel lightweight elastic buffer architecture that minimizes buffering requirements, without sacrificing performance. The integration of the proposed elastic buffering scheme in the NoC router enables the design of new router architectures – both single-cycle and two-stage pipelined – which offer the same performance as baseline VC-based routers, albeit at a significantly lower area/power cost.

1 Introduction

Network-on-Chip technology is already being adopted in the majority of large SoCs for simplifying system integration at the IP-assembly functional verification level – all the way down to physical integration – by alleviating physical routing congestion and simplifying timing closure [1]. NoCs also improve performance by parallelizing communication, offer quality-of-service (QoS) guarantees, and enable flexible system partitioning. The majority of these NoC features can be satisfied by the use of virtual channels (VCs). A physical channel can be used in a time-multiplexed manner by different VCs, provided that each VC owns a separate buffer space [2]. VC-based architectures enable traffic separation and isolation by assigning different traffic classes to different VCs, and they reduce on-chip physical routing congestion by trading off physical channel width and the number of supported VCs, thus, creating a more layout-flexible SoC architecture [3].

The NoC needs to be both scalable, in terms of network functionality and performance, as well as flexible in terms of physical implementation. This requirement motivates us to unify a VC-based architecture that favors NoC scalability with elastic buffering, which eases physical implementation and promises area and power reduction.

Owing to its elastic operation, which is based on simple ready/valid handshakes, elastic buffering is a primitive and simplified form of NoC buffering that can be easily integrated in a plug-and-play manner at the inputs and the outputs of the routers (or inside them) [4], [5], as well as on the network links to act as a buffered repeater. Elastic buffering assumes only one form of handshake on each network channel that cannot distinguish between different flows thus making its operation serial in nature. This feature prevents the interleaving of packets and the isolation of traffic flows, while it complicates deadlock prevention. Due to this limitation, direct support for VCs is abandoned and replaced by multiple physical networks, or implemented via complex and non-scalable hybrid EB/VC buffering architectures [6], [7], [8], which remove the basic property of the EBs to act as stitching elements that can be placed seamlessly anywhere in the NoC.

In this paper, we generalize the operation and the implementation of elastic buffering to support multiple VCs. The proposed architecture, which we call ElastiStore, minimizes the number of buffers per channel (flip-flops, or latches, according to the implementation) close to the absolute minimum of one buffer slot per VC, without sacrificing performance. The scalability of the proposed scheme is demonstrated by the integration of ElastiStore in NoC routers that lead to new architectures – both single-cycle and two-stage pipelined – which offer the same performance as baseline VC-based routers, albeit at a significantly lower area/power cost.

The proposed ElstiStore design is envisioned as an archetypical primitive for future, extremely low-cost NoC router implementations, where the performance and functionality enhancements provided by VCs cannot be sacrificed. In fact, due to protocol-support restrictions, the use of VCs will be mandatory in future Chip Multi-Processors (CMP) employing directorybased cache coherence protocols. These coherence protocols require isolation between the various message classes, in order to avoid protocol-level deadlocks. For example, the MOESI directory-based cache coherence protocol requires at least three virtual networks to prevent protocol-level deadlocks. A virtual network comprises one VC (or a group of VCs) tasked with the handling of a specific message class of the cache coherence protocol [9].

Despite the increased functionality demands, the area/power budgets of individual NoC routers will continue to dwindle as the number of processing elements (and, hence, the NoC size) keeps increasing. The ElastiStore solution aims to precisely reconcile the conflicting and diverging demands of low cost and high performance/functionality.

The rest of the paper is organized as follows: Section II briefly describes elastic flow control, while Section III introduces the ElastiStore architecture. Sections IV and V describe the implementation of ElastiStore and its integration into NoC routers, respectively. Experimental results are presented in Section VII, and conclusions are drawn in Section VIII.