دانلود رایگان ترجمه مقاله طراحی بافرهای کانال باصرفه در مصرف انرژی برای شبکه بر روی تراشه (نشریه IEEE 2009)

طراحی بافرهای کانال باصرفه در مصرف انرژی با مسیریاب کنارگذر کننده برای شبکه بر روی تراشه

Design of Energy-Efficient Channel Buffers with Router Bypassing for Network-on-Chips (NoCs)

Abstract

Network-on-chip (NoC) architectures are fast becoming an attractive solution to address the interconnect delay problems in chip multiprocessors (CMPs). However, increased power dissipation and limited performance improvements have hindered the wide-deployment of NoCs. In this paper, we combine two techniques of adaptive channel buffers and router pipeline bypassing to simultaneously reduce power consumption and improve performance. Power consumption can be decreased by reducing the size of the router buffers. However, as reducing router buffers alone will significantly degrade performance, we compensate by utilizing the newly proposed dual-function channel buffers that allow flits to be stored on wires when required. Network bypassing technique, on the other hand, allows flits to bypass the router pipeline and thereby avoid the router buffers altogether. We combine the two techniques and attempt to keep the flits on the wires from source to destination. Our simulation results of the proposed methodology combining the two techniques, yield a overall power reduction of 62% over the baseline and improve performance (throughput and latency) by more than 10%.

1 Introduction

As the industry builds multi-core architecture involving tens and hundreds of cores in the future, on-chip interconnection networks have emerged as a promising candidate for solving the wire-delay problem facing current chip multiprocessors (CMPs) [1], [2]. However, one of the major research challenges currently faced by on-chip interconnection network designers is that of power dissipation [3]. For example, in the Intel TeraFLOPS processor architecture, the interconnect consumes more than 28% of the total power budget, when the expected power budget should be less than 10% [4]. NoC architectures are characterized by the links for data transmission and the routers for storing, arbitration and switching functions performed by input buffers, arbiters and the crossbar respectively. Power is dissipated both for communicating data across links as well as for switching and storage within the routers [3]. With the increasing need for low power architectures, NoC research has focused on optimizing buffer design [5], [6], [7], minimizing crossbar power [4], [8], and utilizing 3D interconnects [9].

Modular router design ensures that the network bandwidth and storage is shared evenly among all the input channels and packets. This effective sharing of resources (buffer and channel) is achieved by implementing routing, virtual channel (VC) and switch allocation functionalities within the router on a hop-by-hop basis. While the sharing of resources improves the utilization, it also leads to excessive delays seen by every packet/flit traversing from source to destination. Recently, Express Virtual Channel (EVCs) [10] based flow control allowed some network packets to bypass buffering, arbitration and crossbar switching within a single dimension of the on-chip routers, thereby improving latency and reducing power consumption. However, buffer availability through credit based system and VC information has to be explicitly communicated across multiple EVC nodes, which in turn increases the complexity of the design. Recent NOCHI [11] design extended EVCs by allowing buffer/VC information to be broadcast to all nodes using low-swing multi-drop wires which overcomes some of the shortcomings of EVC design. However, NOCHI relies on the use of global wires which requires a separate control plane. This extra control plane adds excessive area. Additionally, broadcasting of communication information across every node adds power (0.6 mW/TX and 0.4 mW/RX). Given the tight power budget, this design maybe suitable where performance is more critical than power consumption such as real-time systems.

Reducing the size of the input router buffers is a natural approach to reduce the power to read/write a flit and area overhead of the router. However, the network performance and flow control is primarily characterized by the input buffers [12]. Recently, iDEAL (inter-router Dual-function Energy and Area-efficient Links) [7], [13] proposed to reduce the size of the buffer and to minimize the performance degradation due to the reduced buffer size, the already existing repeaters along the inter-router channels are doubled as buffers along the channel when required. Research initiatives into optimizing the performance of the repeaters have shown that the repeaters can also be designed to sample and hold data values thereby storing values on the channels [14]. In addition, iDEAL makes use of dynamic buffer allocation to enable a higher buffer occupancy where space is reserved on a per flit basis.