دانلود رایگان ترجمه مقاله ارتباطات بی سیم با استفاده از گرافن برای معماری های گسترده چند هسته ای (نشریه IEEE 2013)

ارتباط بی سیم با استفاده از گرافن برای معماری های گسترده چند هسته ای

Graphene-enabled Wireless Communication for Massive Multicore Architectures

Abstract

Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main bottleneck is foreseen to migrate from computation to communication, efficient and scalable means of inter-core communication are crucial for guaranteeing steady performance improvements in many-core processors. As the number of cores grows, it remains unclear whether initial proposals, such as the Network-on-Chip (NoC) paradigm, will meet the stringent requirements of this scenario. This position paper presents a new research area where massive multicore architectures have wireless communication capabilities at the core level. This goal is feasible by using graphene-based planar antennas, which can radiate signals at the Terahertz band while utilizing lower chip area than its metallic counterparts. To the best of our knowledge, this is the first work that discusses the utilization of graphene-enabled wireless communication for massive multicore processors. Such wireless systems enable broadcasting, multicasting, all-to-all communication, as well as significantly reduce many of the issues present in massively multicore environments, such as data coherency, consistency, synchronization and communication problems. Several open research challenges are pointed out related to implementation, communications and multicore architectures, which pave the way for future research in this multidisciplinary area.

1 Introduction

ircuits, i.e., precise manufacturing techniques, have enabled a steady reduction in the size of transistors. Such tendency has allowed the integration of more transistors on the same chip and resulted in a very high performance increase and cost decrease per transistor. As the level of integration approaches Ultra-Large-Scale Integration (ULSI), the intra-chip communication latency and power consumption become major barriers that prevent the continuation of the trend set by the Moore’s Law.

Indeed, the main reasons for the diminishing performance returns of such downscaling trend are as follows. By reducing the width of the on-chip wires, their resistance and therefore the resistive-capacitive (RC) delay are significantly increased. Also, by taking into account the increased clock frequencies imposing reduced symbol times, the charging and discharging the wire within the allotted time becomes a very challenging problem. Finally, the dynamic power demand of a Complementary Metal Oxide Semiconductor (CMOS) transistor grows proportionally to its operation frequency and quadratically to the circuit voltage, justifying the need for lowvoltage and frequency-limited designs. Graphene, thanks to its extremely promising properties, could enable the devising of transistors with higher speed and lower energy consumption than traditional CMOS devices. However, such transistors are, thus far, projected for its application in RF circuits rather than in digital computation, due to the intrinsic absence of band gap in graphene [1].

Since better performance is no longer achievable through an increase in clock frequency due to the reasons pointed out above, the natural trend in microprocessor architecture design is to improve the performance by means of parallel architectures. Parallelization is achieved by interconnecting several independent processors forming a Chip Multiprocessor (CMP), and has led towards the recent emergence of multicore and manycore, i.e., more than 16 cores, processors. The main performance bottleneck in these systems is currently defined by the intra-chip communication requirements set by coherency or synchronization, among other common and necessary operations in multicore environments. In this context, the Network-on-Chip (NoC) paradigm was proposed to increase the performance of CMP systems by providing scalable and efficient inter-core communication through wireline routed interconnections. This approach arose as opposed to the traditional bus-based architectures, which scale poorly in terms of delay and energy efficiency due to its time division multiplexing nature, when the number of cores is increased.