|عنوان فارسی مقاله:||بررسی همه SoC های برنامه ریزی Zynq–7000|
|عنوان انگلیسی مقاله:||Zynq-7000 All Programmable SoC Overview|
|رشته های مرتبط:||مهندسی برق و مهندسی کامپیوتر، معماری سیستمهای کامپیوتری، سخت افزار، سیستمهای الکترونیک دیجیتال و مهندسی الکترونیک|
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بوت PS و پیکربندی دستگاه
بخشی از مقاله انگلیسی:
PS Boot and Device Configuration
Zynq-7000 and Zynq-7000S devices use a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication. Upon reset, the device mode pins are read to determine the primary boot device to be used: NOR, NAND, Quad-SPI, SD, or JTAG. JTAG can only be used as a non-secure boot source and is intended for debugging purposes. One of the ARM Cortex-A9 CPUs executes code out of on-chip ROM and copies the first stage boot loader (FSBL) from the boot device to the OCM. After copying the FSBL to OCM, the processor executes the FSBL. Xilinx supplies example FSBLs or users can create their own. The FSBL initiates the boot of the PS and can load and configure the PL, or configuration of the PL can be deferred to a later stage. The FSBL typically loads either a user application or an optional second stage boot loader (SSBL) such as U-Boot. Users obtain the SSBL from Xilinx or a third party, or they can create their own SSBL. The SSBL continues the boot process by loading code from any of the primary boot devices or from other sources such as USB, Ethernet, etc. If the FSBL did not configure the PL, the SSBL can do so, or again, the configuration can be deferred to a later stage. The static memory interface controller (NAND, NOR, or Quad-SPI) is configured using default settings. To improve device configuration speed, these settings can be modified by information provided in the boot image header. The ROM boot image is not user readable or callable after boot.
Hardware and Software Debug Support
The debug system used in the Zynq-7000 family is based on ARM’s CoreSight architecture. It uses ARM CoreSight components including an embedded trace buffer (ETB), a program trace macrocell (PTM), and an instrument trace macrocell (ITM). This enables instruction trace features as well as hardware breakpoints and triggers. The programmable logic can be debugged with the integrated logic analyzer.
Two JTAG ports are available and can be chained together or used separately. When chained together, a single port is used for ARM processor code downloads and run-time control operations, PL configuration, and PL debug with the ChipScope™ Pro embedded logic analyzer. This enables tools such as the Xilinx Software Development Kit (SDK) and ChipScope Pro analyzer to share a single download cable from Xilinx. When the JTAG chain is split, one port is used for PS support, including direct access to the ARM DAP interface. This CoreSight interface enables the use of ARM-compliant debug and software development tools such as Development Studio 5 (DS-5™). The other JTAG port can then be used by the Xilinx FPGA tools for access to the PL, including configuration bitstream downloads and PL debug with the integrated logic analyzer. In this mode, users can download to, and debug the PL in the same manner as a stand-alone FPGA.
The PS and PL reside on different power planes. This enables the PS and PL to be connected to independent power rails, each with its own dedicated power supply pins. If PL power-off mode is not needed, the user can tie the PS and PL power rails together. When the PS is in power-off mode, it holds the PL in a permanent reset condition. The power control for the PL is accomplished through external pins to the PL. External power management circuitry can be used to control power. The external power management circuitry could be controlled by software and the PS GPIO.